Patent · US Active

Uniform layouts for SRAM and register file bit cells

US11737253B2 · kind B2 · utility

0Cited by

4References

8Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zheng Guo · Portland, US
Clifford L. Ong · Portland, US
Eric A. Karl · Portland, US
Mark Bohr · Beaverton, US

Key dates

Filing date	Jun 22, 2017
Grant date	Aug 22, 2023
Priority date	—
Expiry date	Oct 29, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.