Heterogeneous system on a chip scheduler with learning agent
US11740933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jun 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.