Request ordering in a cache
US11741009B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.