Efficiently striping ordered PCIe writes across multiple socket-to-socket links
US11741028B1 · kind B1 · utility
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Key dates
| Filing date | May 20, 2022 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | May 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Innovative techniques to efficient stripe ordered writes across multiple socket-to-socket links. The ordered writes may be PCIe ordered writes. Each socket-to-socket write (or remote write) for an address may be converted into two transactions. The first transaction may ensure that coherency for the address is ensured. The second transaction may be the actual request transaction to write the data of the address. In so doing, when multiple remote writes are involved, the remote writes may be distributed over multiple socket-to-socket links to maximize bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.