Voltage-controlled gain-cell magnetic memory
US11742011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Mar 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 MΩ, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.