Memory device and multi-pass program operation thereof
US11742037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Dec 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each of the row of target memory cells is programmed into one of 2N/m intermediate levels based on the piece of N-bits data to be stored in the target memory cell, where m is an integer greater than 1. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the piece of N-bits data to be stored in the target memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.