Small-area side-capacitor read-only memory device, memory array and method for operating the same
US11742039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2022 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Apr 27, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.