Dynamic random-access memory (DRAM) training acceleration
US11742043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Nov 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.