Memory built-in self-test with adjustable pause time
US11742044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.