Sensor for performance variation of memory read and write characteristics
US11742051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Oct 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.