Patent · US Active

Interconnect structure fabricated using lithographic and deposition processes

US11742284B2 · kind B2 · utility

0Cited by

1References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zhicheng Ding · Shanghai, CN
Bin Liu · Fishers, US
Yong She · Shanghai, CN
Zhijun Xu · Shanghai, CN

Key dates

Filing date	Dec 12, 2018
Grant date	Aug 29, 2023
Priority date	—
Expiry date	Dec 12, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.