Three dimensional vertically structured electronic devices

US11742424B2 · kind B2 · utility

Assignee

• Lawrence Livermore National Security, LLC · US

Inventors

• Adam Conway · Livermore, US
• Sara Elizabeth Harrison · Livermore, US
• Rebecca J. Nikolic · Oakland, US
• Qinghui Shao · Fremont, US
• Lars Voss · Livermore, US

Key dates

• Filing date: Jan 7, 2021
• Grant date: Aug 29, 2023
• Expiry date: Mar 1, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.