Gate drivers for stacked transistor amplifiers
US11742802B2 · kind B2 · utility
1Cited by
31References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Nov 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/522
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.