Fabrication of embedded memory devices utilizing a self assembled monolayer
US11744083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2019 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jul 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.