Semiconductor devices and methods of forming semiconductor devices with logic and memory regions insulation layers
US11744085B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 10, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jan 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first insulating layer; a second insulating layer arranged over the first insulating layer; a memory structure arranged within a memory region and including a resistance changing memory element within the first insulating layer; and a logic structure arranged within a logic region. In the memory region, the first insulating layer may contact the second insulating layer and in the logic region, the semiconductor device may further include a stop layer arranged between the first insulating layer and the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.