Three-dimensional resistive memory device
US11744087B2 · kind B2 · utility
1Cited by
2References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Feb 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/066
Abstract
A resistive memory device includes a vertical word line pillar, a plurality of resistive layers, a gate insulation layer, and a channel layer. The vertical word line pillar is formed on a semiconductor substrate. The resistive layers are stacked at both sides of the vertical word line pillar. The gate insulation layer is interposed between the vertical word line pillar and the resistive layers. The channel layer is arranged between the gate insulation layer and the resistive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.