Concurrent processing of translation entry invalidation requests in a processor core
US11748267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2022 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of entries including address translation information are buffered in a data structure in a processor core. At least first and second translation entry invalidation requests specifying different first and second addresses are checked against all of the entries in the data structure. The checking includes accessing and checking at least a first entry in the data structure for an address match with the first address but not the second address, thereafter concurrently checking at least a second entry for an address match with both the first and second addresses, and thereafter completing checking for the first address and accessing and checking the first entry for an address match with the second address but not the first address. The processor core invalidates any entry in the data structure for which the checking detects an address match.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.