Electronic package and method for manufacturing the same
US11749583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Jan 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.