Patent · US Active

Memory circuits

US11749664B2 · kind B2 · utility

1Cited by

2References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Yi-Ching Liu · Hsinchu, TW
Yih Wang · Hsinchu, TW
Chia-En Huang · Xinfeng, TW

Key dates

Filing date	Jul 12, 2022
Grant date	Sep 5, 2023
Priority date	—
Expiry date	Jul 12, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15192
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.