Process for manufacturing a relaxed GaN/InGaN structure
US11749779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2020 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Apr 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically conductive doped GaN layer locally covered with InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) connecting the electrically conductive doped GaN layer and a counter-electrode (500) to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second electrode to porosify the doped InGaN layer, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.