Semiconductor memory device
US11751378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Jul 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.