Patent · US Active

Embedded memory pillar

US11751492B2 · kind B2 · utility

0Cited by
10References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 24, 2021
Grant dateSep 5, 2023
Priority date
Expiry dateApr 22, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10N70/841

Abstract

A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.