Computer architecture having selectable, parallel and serial communication channels between processors and memory
US11755060B2 · kind B2 · utility
1Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2018 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Aug 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.