Hao Wang
15Patents
3h-index
31Co-inventors
56Inventor score
Filing activity: Mar 22, 2005 → Sep 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8065728B2 | Malware prevention system monitoring kernel events | Physics | 36 | Active |
| US10108220B2 | Computer architecture having selectable, parallel and serial communication channels between processors and memory | Physics | 11 | Active |
| US9501227B2 | Memory controller for heterogeneous computer | Physics | 3 | Active |
| US10089458B2 | Separate, disposable execution environment for accessing unverified content | Physics | 2 | Active |
| US9665290B2 | Memory controller for heterogeneous computer | Physics | 1 | Active |
| US9959205B2 | Shared row buffer system for asymmetric memory | Physics | 1 | Active |
| US11755060B2 | Computer architecture having selectable, parallel and serial communication channels between processors and memory | Physics | 1 | Active |
| US7240255B2 | Area efficient BIST system for memories | Physics | 0 | Expired |
| US11803511B2 | Methods and systems for ordering operations on a file system having a hierarchical namespace | Physics | 0 | Active |
| US12373139B2 | Systems and methods for input/output dispatch | Physics | 0 | Active |
| US12222856B2 | Memory controller and method for controlling output of debug messages | Physics | 0 | Active |
| US10877773B2 | Distribution of a software client application towards a client computing device | Electricity | 0 | Active |
| US11740909B2 | Secure speculative execution of instructions | Physics | 0 | Active |
| US12326838B2 | Implementation for efficient log storage | Physics | 0 | Active |
| US12140992B2 | Computer architecture having selectable parallel and serial communication channels between processors and memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.