Storing a logical-to-physical mapping in NAND memory
US11755495B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Mar 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.