Switches to reduce routing rails of memory system
US11756591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Aug 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.