Memory device supporting DBI interface and operating method of memory device
US11756592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Nov 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.