Semiconductor device with non-volatile memory cell and manufacturing method thereof
US11757011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.