Three-dimensional semiconductor device and method of fabricating the same

US11758740B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chang-Tsung Pai · Taichung, TW
• Chiung-Lin Hsu · Taichung, TW
• Yu-Ting Chen · Taipei, TW
• Ming-Che Lin · Zhuolan Township, TW
• Chi-Ching Liu · Taichung, TW

Key dates

• Filing date: Apr 7, 2021
• Grant date: Sep 12, 2023
• Expiry date: Apr 3, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.