Signal receiver with skew-tolerant strobe gating
US11763865B1 · kind B1 · utility
1Cited by
19References
21Claims
0Family size
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Key dates
| Filing date | Aug 26, 2021 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Sep 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.