Power architecture for non-volatile memory
US11763895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jul 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.