Package assembly for plating with selective molding
US11764075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.