Semiconductor device
US11764261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2022 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Feb 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.