Compaction of architected registers in a simultaneous multithreading processor
US11768684B2 · kind B2 · utility
0Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2020 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Oct 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.