System and method for transparent register data error detection and correction via a communication bus
US11768731B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2019 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.