Memory sub-system with a virtualized bus and internal logic to perform a machine learning operation
US11769076B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Apr 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory component includes a memory region to store a machine learning model and input data and another memory region to store host data from a host system. A controller can be coupled to the memory component and can include in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and a decoder can receive the additional data from the bus and can transmit the additional data to the other memory region or the in-memory logic of the controller based on a characteristic of the additional data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.