Memory device transmitting and receiving data at high speed and low power
US11769547B2 · kind B2 · utility
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10References
19Claims
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Key dates
| Filing date | Mar 2, 2022 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Mar 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.