Dual trace thickness for single layer routing

US11769719B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jonathan L. Rosch · Mesa, US
• Wei-Lun Kane Jen · Chandler, US
• Cheng Xu · Chandler, US
• Liwei Cheng · Chandler, US
• Andrew J. Brown · Brier, US
• Yikang Deng · New York, US

Key dates

• Filing date: Jun 25, 2018
• Grant date: Sep 26, 2023
• Expiry date: Jun 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K2201/09827
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.