Package substrate
US11769733B2 · kind B2 · utility
0Cited by
0References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2022 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Oct 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.