Prioritization of threads in a simultaneous multithreading processor core
US11775337B2 · kind B2 · utility
0Cited by
9References
17Claims
0Family size
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Key dates
| Filing date | Sep 2, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Dec 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first instruction for processing by a processor core is received. Whether the instruction is a larx is determined. Responsive to determining the instruction is a larx, whether a cacheline associated with the larx is locked is determined. Responsive to determining the cacheline associated with the larx is not locked, the cacheline associated with the larx is locked and a counter associated with a first thread of the processor core is started. The first thread is processing the first instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.