Memory device with source line control
US11776595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Jan 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.