Pulsed bias for power-up or read recovery
US11776634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device is provided that applies pulsed biasing during power-up or read recovery. The storage device includes a memory and a controller. The memory includes a block having a word line and cells coupled to the word line. The controller applies a voltage pulse to the word line during power-up or in response to a read error. The voltage pulse may include an amplitude and a pulse width that are each a function of a number of P/E cycles of the block. The controller may also perform pulsed biasing during both power-up and read recovery by applying one or more first voltage pulses to the word line during power-up and one or more second voltage pulses to the word line in response to a read error. As a result, lower bit error rates due to wider Vt margins may occur and system power may be saved over constant biasing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.