Inventor · Milpitas, CA, US

Muhammad Masuduzzaman

26Patents
3h-index
33Co-inventors
55Inventor score

Filing activity: Apr 30, 2015 → Jul 24, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US10014063B2 Smart skip verify mode for programming a memory device Physics 33 Active
US9842657B1 Multi-state program using controlled weak boosting for non-volatile memory Physics 15 Active
US9779832B1 Pulsed control line biasing in memory Physics 5 Active
US9711211B2 Dynamic threshold voltage compaction for non-volatile memory Physics 2 Active
US11139038B1 Neighboring or logical minus word line dependent verify with sense time in programming of non-volatile memory Electricity 1 Active
US10312342B2 NEMS devices with series ferroelectric negative capacitor Electricity 1 Active
US11475967B1 Modified verify in a memory device Electricity 1 Active
US9755041B2 NEMS devices with series ferroelectric negative capacitor Electricity 1 Active
US12205657B2 Hybrid smart verify for QLC/TLC die Physics 0 Active
US11423993B2 Bi-directional sensing in a memory Physics 0 Active
US12354704B2 Active current consumption save mode for non-volatile memory using fast programming Physics 0 Active
US10984876B2 Temperature based programming in memory Physics 0 Active
US11830555B2 Bias for data retention in fuse ROM and flash memory Physics 0 Active
US12327046B2 Data retention-specific refresh read Physics 0 Active
US11081184B2 Method of concurrent multi-state programming of non-volatile memory with bit line voltage step up Physics 0 Active
US12057175B2 Memory apparatus and method of operation using state dependent strobe tier scan to reduce peak ICC Electricity 0 Active
US10217520B2 Pulsed control line biasing in memory Physics 0 Active
US12057168B2 Neighbor aware multi-bias programming in scaled BICS Electricity 0 Active
US12079496B2 Bundle multiple timing parameters for fast SLC programming Physics 0 Active
US11887677B2 Quick pass write programming techniques in a memory device Electricity 0 Active
US11417393B2 Two-stage programming using variable step voltage (DVPGM) for non-volatile memory structures Physics 0 Active
US11574693B2 Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention Physics 0 Active
US12142315B2 Low power multi-level cell (MLC) programming in non-volatile memory structures Physics 0 Active
US11776634B2 Pulsed bias for power-up or read recovery Physics 0 Active
US12112800B2 High speed multi-level cell (MLC) programming in non-volatile memory structures Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.