System and method for parallel memory test
US11776656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Nov 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.