Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method
US11776820B2 · kind B2 · utility
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15References
17Claims
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Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Sep 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the application provide a vertical interconnection structure and a manufacturing method thereof, a packaged chip, and a chip packaging method. Conductive pillars are formed on a first surface of a substrate. A first insulated support layer wrapping the conductive pillars is formed on the first surface of the substrate. The conductive pillars are located in the first insulated support layer. An upper surface of the conductive pillar that is away from the substrate is not covered by the first insulated support layer. Then the substrate is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.