Xiaoyun WEI
4Patents
0h-index
10Co-inventors
31Inventor score
Filing activity: Sep 6, 2017 → Dec 23, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11776820B2 | Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method | Electricity | 0 | Active |
| US12341116B2 | Chip package structure, preparation method, and electronic device | Electricity | 0 | Active |
| US11862529B2 | Chip and manufacturing method thereof, and electronic device | Electricity | 0 | Active |
| US11322701B2 | High dielectric constant composite material and application thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.