Corner guard for improved electroplated first level interconnect bump height range

US11776864B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jacob VEHONSKY · Gilbert, US
• Nicholas S. Haehn · Scottsdale, US
• Thomas HEATON · Mesa, US
• Steve Cho · Chandler, US
• Rahul Jain · Chandler, US
• Tarek A. Ibrahim · Mesa, US
• Antariksh Rao Pratap SINGH · Gilbert, US
• Edvin Cetegen · Chandler, US
• Nicholas Neal · Gilbert, US
• Sergio Antonio Chan Arguedas · Chandler, US

Key dates

• Filing date: Jul 15, 2019
• Grant date: Oct 3, 2023
• Expiry date: Dec 27, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/381
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.