Steve Cho
18Patents
3h-index
43Co-inventors
52Inventor score
Filing activity: Sep 15, 2016 → Apr 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10431537B1 | Electromigration resistant and profile consistent contact arrays | Electricity | 8 | Active |
| US11373972B2 | Microelectronic structures including bridges | Electricity | 8 | Active |
| US10297563B2 | Copper seed layer and nickel-tin microbump structures | Electricity | 3 | Active |
| US11488918B2 | Surface finishes with low rBTV for fine and mixed bump pitch architectures | Electricity | 1 | Active |
| US11309239B2 | Electromigration resistant and profile consistent contact arrays | Electricity | 1 | Active |
| US11088103B2 | First layer interconnect first on carrier approach for EMIB patch | Electricity | 1 | Active |
| US12009271B2 | Protruding SN substrate features for epoxy flow control | Electricity | 1 | Active |
| US11699648B2 | Electromigration resistant and profile consistent contact arrays | Electricity | 0 | Active |
| US12362250B2 | Protruding SN substrate features for epoxy flow control | Electricity | 0 | Active |
| US12341117B2 | Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates | Electricity | 0 | Active |
| US11776864B2 | Corner guard for improved electroplated first level interconnect bump height range | Electricity | 0 | Active |
| US12068172B2 | Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages | Electricity | 0 | Active |
| US10854541B2 | Electromigration resistant and profile consistent contact arrays | Electricity | 0 | Active |
| US11935857B2 | Surface finishes with low RBTV for fine and mixed bump pitch architectures | Electricity | 0 | Active |
| US12354992B2 | First layer interconnect first on carrier approach for EMIB patch | Electricity | 0 | Active |
| US12334453B2 | Soldered metallic reservoirs for enhanced transient and steady-state thermal performance | Electricity | 0 | Active |
| US12334422B2 | Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates | Electricity | 0 | Active |
| US11735558B2 | Microelectronic structures including bridges | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.