Three-dimensional stacked package structure with micro-channel heat dissipation structure and packaging method thereof
US11776879B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/182
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.