Semiconductor chip including low-k dielectric layer
US11776894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | May 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/05684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.